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Dual-Channel, 14-Bit CCD Signal Processor with Precision TimingTM Core AD9942
FEATURES
40 MHz correlated double sampler (CDS) 0 dB to 18 dB, 9-bit variable gain amplifier (VGA) 40 MSPS analog-to-digital converter (ADC) Optical black clamp (CLPOB) with variable level control Complete on-chip timing driver Precision Timing core with <550 ps resolution On-chip 3 V horizontal and RG drivers 4-phase H-clock mode 100-lead, 9 mm x 9 mm, CSP_BGA package
GENERAL DESCRIPTION
The AD9942 is a highly integrated dual-channel CCD signal processor for digital still camera applications. Each channel is specified at pixel rates of up to 40 MHz. The AD9942 consists of a complete analog front end with analog-to-digital conversion, combined with a programmable timing driver. The Precision Timing core allows high speed clocks to be adjusted with 550 ps resolution. The analog front end uses black level clamping and includes a VGA, a 40 MSPS ADC, and a CDS. The timing driver provides the high speed CCD clock drivers for RG_A and RG_B, as well as the H1A to H4A and H1B to H4B outputs. The 6-wire serial interface is used to program the AD9942. Available in a space-saving, 9 mm x 9 mm, CSP_BGA package, the AD9942 is specified over an operating temperature range of -25C to +85C.
APPLICATIONS
Signal processor for dual-channel CCD outputs Digital still cameras Digital video cameras High speed digital imaging applications
FUNCTIONAL BLOCK DIAGRAM
REFT_A REFB_A REFT_B REFB_B
AD9942
VREF_A
VREF_B 14
CCDIN_A
CDS
VGA 0dB ~ 18dB
ADC CLAMP CLAMP 0dB ~ 18dB
DOUT_A
CCDIN_B
CDS
VGA
ADC
14
DOUT_B
INTERNAL CLOCKS RG_A RG_B H1A TO H4A H1B TO H4B 4 4 SYNC GENERATOR INTERNAL REGISTERS SCK_A SCK_B
05240-001
HORIZONTAL DRIVERS
PRECISION TIMING CORE
CLI_A CLI_B
HD_A VD_A HD_B VD_B
SL_A SDATA_A SL_B SDATA_B
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD9942 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 General Specifications ................................................................. 3 Digital Specifications ................................................................... 4 Analog Specifications................................................................... 5 Channel-to-Channel Specifications........................................... 6 Timing Specifications .................................................................. 7 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Terminology .................................................................................... 11 Equivalent Input/Output Circuits ................................................ 12 Typical Performance Characteristics ........................................... 13 System Overview ............................................................................ 14 Serial Interface Timing .................................................................. 15 Complete Register Listing ......................................................... 16 Channel A and Channel B Precision Timing ............................... 19 High Speed Timing Generation ............................................... 19 Timing Resolution...................................................................... 19 High Speed Clock Programmability........................................ 19 H Driver and RG Outputs......................................................... 21 Digital Data Outputs.................................................................. 21 Channel A and Channel B Horizontal Clamping and Blanking ....22 Individual CLPOB and PBLK Sequences................................ 22 Individual HBLK Sequences..................................................... 22 Channel A and Channel B Special HBLK Patterns.................... 24 Horizontal Sequence Control ................................................... 24 H-Counter Synchronization ..................................................... 25 Channel A and Channel B Power-Up Procedure....................... 26 Channel A and Channel B Analog Front End Operation......... 27 DC Restore .................................................................................. 27 Correlated Double Sampler ...................................................... 27 Channel A and Channel B Variable Gain Amplifier ............. 28 Channel A and Channel B ADC .............................................. 28 Channel A and Channel B CLPOB.......................................... 28 Channel A and Channel B Digital Data Outputs................... 28 Applications Information .............................................................. 29 Circuit Configuration ................................................................ 29 Grounding/Decoupling Recommendations ........................... 29 Driving the CLI Input................................................................ 31 Horizontal Timing Sequence Example.................................... 31 Outline Dimensions ....................................................................... 33 Ordering Guide .......................................................................... 33
REVISION HISTORY
8/06--Rev. 0 to Rev. A Changes to Table 3............................................................................ 5 Changes to Table 13........................................................................ 17 Change to Channel A and Channel B Variable Gain Amplifier Section............................................... 28 Updated Outline Dimensions ....................................................... 33 1/05--Revision 0: Initial Version
Rev. A | Page 2 of 36
AD9942 SPECIFICATIONS
GENERAL SPECIFICATIONS
X = A, B. Table 1.
Parameter TEMPERATURE RANGE Operating Storage MAXIMUM CLOCK RATE POWER SUPPLY VOLTAGE AVDD_X, TCVDD_X (AFE, Timing Core) HVDD_X (H1X to H4X Drivers) RGVDD_X (RG_X Driver) DRVDD_X (D0 to D13 Drivers) DVDD_X (Digital) POWER DISSIPATION FOR EACH CHANNEL (40 MHz, 3 V Supplies, 100 pF H1X to H4X Loading, 10 pF RG_X Loading) Power from AVDD_X Power from TCVDD_X Power from HVDD_X 1 Power from RGVDD_X Power from DRVDD_X Power from DVDD_X Total Shutdown Mode
1
Min -25 -65 40 2.7 2.7 2.7 2.7 2.7
Typ
Max +85 +150
Unit C C MHz V V V V V
3.0 3.0 3.0 3.0 3.0
3.6 3.6 3.6 3.6 3.6
110 33 160 13 15 40 2
mW mW mW mW mW mW mW
Total HVDD_X Power = [(CLOAD) x (HVDD_X) x (Pixel Frequency)] x (HVDD_X) x (Number of Horizontal Outputs Used).
Rev. A | Page 3 of 36
AD9942
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD_X = DVDD_X = DRVDD_X = HVDD_X = RGVDD_X = 2.7 V, CL = 20 pF, unless otherwise noted. X = A, B. Table 2.
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA CLI INPUT High Level Input Voltage (TCVDD_X/2 + 0.5 V) Low Level Input Voltage RG_X AND H1X TO H4X DRIVER OUTPUTS High Level Output Voltage (RGVDD_X - 0.5 V and HVDD_X - 0.5 V) Low Level Output Voltage Maximum Output Current (Programmable) Maximum Load Capacitance Symbol VIH VIL IIH IIL CIN VOH VOL VIH - CLI VIL - CLI VOH VOL Min 2.1 0.6 10 10 10 2.2 0.5 1.85 0.85 2.2 0.5 30 100 Typ Max Unit V V A A pF V V V V V V mA pF
Rev. A | Page 4 of 36
AD9942
ANALOG SPECIFICATIONS
TMIN to TMAX, AVDD_X = DVDD_X = 3.0 V, fCLI = 40 MHz, typical timing specifications, unless otherwise noted. X = A, B. Table 3.
Parameter CDS Gain Allowable CCD Reset Transient 1 Max Input Range Before Saturation Max CCD Black Pixel Amplitude VARIABLE GAIN AMPLIFIER (VGA_X) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Min Gain (Code 0) Max Gain (Code 511) CLPOB Clamp Level Resolution Clamp Level Min Clamp Level Max Clamp Level CHN_A AND CHN_B ADC Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT_X) Reference Bottom Voltage (REFB_X) SYSTEM PERFORMANCE VGA Gain Accuracy Min Gain (Code 0) Max Gain (Code 511) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR)
1
Min
Typ 0 500
Max
Unit dB mV V p-p mV
Notes
1.0 100
Measured at 12 dB VGA gain (Typ = 70 mV at 15 dB and 50 mV at 18 dB)
1.0 2.0 512 Guaranteed 0 18 256 0 1023 -1.0 0.5 Guaranteed 2.0 2.0 1.0 +1.0
V p-p V p-p Steps
dB dB Steps LSB LSB LSB V V V Specifications include entire signal chain 4 LSB/step Measured at ADC output
-0.5 17.5
0 18 0.15 3 50
+0.5 18.5
dB dB % LSB rms dB
12 dB gain applied AC grounded input, 6 dB gain applied Measured with step change on supply
Input signal characteristics defined as follows:
100mV MAX OPTICAL BLACK PIXEL
1V MAX INPUT SIGNAL RANGE
05240-099
500mV TYP RESET TRANSIENT
Rev. A | Page 5 of 36
AD9942
CHANNEL-TO-CHANNEL SPECIFICATIONS
TMIN to TMAX, AVDD_X = DVDD_X = 3.0 V, fCLI = 40 MHz, typical timing specifications, unless otherwise noted. X = A, B. Table 4.
Parameter CHANNEL A/CHANNEL B OUTPUT CODE MATCHING ERROR 1 CROSSTALK ERROR Channel A to Channel B Channel B to Channel A
1
Min
Typ <1.0%
Max
Unit
Notes VGA = 6 dB, 12 dB, and 18 dB conditions. VGA = 6 dB, 12 dB, and 18 dB conditions. Full-scale step applied to Channel A while measuring response on Channel B. Full-scale step applied to Channel B while measuring response on Channel A.
-84 -84
dB dB
Matching error calculated using a ramp input applied to Channel A and Channel B simultaneously. Typical Channel A/Channel B error is <1.0% at each output code.
Rev. A | Page 6 of 36
AD9942
TIMING SPECIFICATIONS
CL = 20 pF, fCLI = 40 MHz, serial timing in Figure 14 and Figure 15, unless otherwise noted. X = A, B. Table 5.
Parameter MASTER CLOCK (CLI_X) (See Figure 16) CLI_X Clock Period CLI_X High/Low Pulse Width Delay from CLI_X to Internal Pixel Period Position (See Figure 16) CLPOB_X PULSE WIDTH (Programmable) 1 SAMPLE CLOCKS (See Figure 17) SHP_X Rising Edge to SHD_X Rising Edge DATA OUTPUTS (See Figure 19 and Figure 20) Output Delay from Programmed Edge Pipeline Delay SERIAL INTERFACE Maximum SCK_X Frequency SL_X to SCK_X Setup Time SCK to SL_X Hold Time SDATA_X Valid to SCK_X Rising Edge Setup SCK_X Falling Edge to SDATA_X Valid Hold SCK_X Falling Edge to SDATA_X Valid Read
1
Symbol
Min 25.0 10.0 2 11.2
Typ
Max
Unit ns ns ns Pixels ns ns Cycles MHz ns ns ns ns ns
tADC tCLIDLY tCOB tS1 tOD
12.5 6 20 12.5 6 11
15.0
fSCLK tLS tLH tDS tDH tDV
10 10 10 10 10 10
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Rev. A | Page 7 of 36
AD9942 ABSOLUTE MAXIMUM RATINGS
Table 6. Ratings (X = A, B)
Parameter AVDD_X and TCVDD_X to AVSS_X HVDD_X and RGVDD_X to HVSS_X and RGVSS_X DVDD_X and DRVDD_X to DVSS_X and DRVSS_X Any VSS_X to Any VSS_X Digital Outputs to DRVSS_X SCK_X, SL_X, and SDATA_X to DVSS_X RG_X to RGVSS_X H1X to H4X to HVSS_X REFT_X, REFB_X, and CCDIN_X to AVSS_X Junction Temperature Lead Temperature (10 sec) Rating -0.3 V to +3.9 V -0.3 V to +3.9 V -0.3 V to +3.9 V -0.3 V to +0.3 V -0.3 V to DRVDD + 0.3 V -0.3 V to DVDD + 0.3 V -0.3 V to RGVDD + 0.3 V -0.3 V to HVDD + 0.3 V -0.3 V to AVDD + 0.3 V 150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
100-lead, 9 mm x 9 mm, CSP_BGA package: JA = 38.3C/W 1
1
JA is measured using a 4-layer PCB with the exposed paddle soldered to the board.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 8 of 36
AD9942 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A1 CORNER INDEX AREA 1 A B C D E F G H J K
05240-002
2
3
4
5
6
7
8
9 10
AD9942
TOP VIEW (Not to Scale)
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Ball Location B2 C2 D2 C1 D1 A1 F4 F3 D4 D3 B4 J2 K3 E3 E4 C3 C4 B3 A4 B1 A2 F2 F1 E2 E1 B8 C8 D8 C7 D7 A7 F10 F9 D10 Mnemonic SL_A SDATA_A SCK_A REFT_A REFB_A CCDIN_A H1A H2A H3A H4A RG_A DRVSS_A DRVDD_A HVSS_A HVDD_A RGVSS_A RGVDD_A TCVSS_A TCVDD_A AVSS_A AVDD_A DVSS_A DVDD_A VD_A HD_A SL_B SDATA_B SCK_B REFT_B REFB_B CCDIN_B H1B H2B H3B Type 1 DI DI DI AO AO AI DO DO DO DO DO P P P P P P P P P P P P DI DI DI DI DI AO AO AI DO DO DO Description 6-Wire Serial Load for Channel A 6-Wire Serial Data for Channel A 6-Wire Serial Clock for Channel A Reference Top Decoupling for Channel A (decouple with 1.0 F to AVSS_A) Reference Bottom Decoupling for Channel A (decouple with 1.0 F to AVSS_A) Analog Input for Channel A CCD Signal (connect through series 0.1 F capacitor) CCD Horizontal Clock 1 for Channel A CCD Horizontal Clock 2 for Channel A CCD Horizontal Clock 3 for Channel A CCD Horizontal Clock 4 for Channel A CCD Reset Gate Clock for Channel A Digital Driver Ground for Channel A Digital Driver Supply for Channel A H1A to H4A Driver Ground for Channel A H1A to H4A Driver Supply for Channel A RG_A Driver Ground for Channel A RG_A Driver Supply for Channel A Analog Ground for Channel A Timing Core Analog Supply for Channel A Timing Core Analog Ground for Channel A Analog Ground for Channel A Digital Ground for Channel A Digital Supply for Channel A Vertical Sync Pulse for Channel A Horizontal Sync Pulse for Channel A 6-Wire Serial Load for Channel B 6-Wire Serial Data for Channel B 6-Wire Serial Clock for Channel B Reference Top Decoupling for Channel B (decouple with 1.0 F to AVSS_B) Reference Bottom Decoupling for Channel B (decouple with 1.0 F to AVSS_B) Analog Input for Channel B CCD Signal (connect through series 0.1 F capacitor) CCD Horizontal Clock 1 for Channel B CCD Horizontal Clock 2 for Channel B CCD Horizontal Clock 3 for Channel B
Rev. A | Page 9 of 36
AD9942
Ball Location D9 B10 J8 K9 E9 E10 C9 C10 B9 A10 B7 A8 F8 F7 E8 E7 A3 G1 H1 J1 K1 G2 H2 K2 G3 H3 J3 K4 J4 H4 G4 A5, B5, C5, D5, E5, F5, G5, H5, J5, K5, A6, B6, C6, D6, E6, F6, G6, H6, J6, K6 A9 G7 H7 J7 K7 G8 H8 K8 G9 H9 J9 K10 J10 H10 G10
1
Mnemonic H4B RG_B DRVSS_B DRVDD_B HVSS_B HVDD_B RGVSS_B RGVDD_B TCVSS_B TCVDD_B AVSS_B AVDD_B DVSS_B DVDD_B VD_B HD_B CLI_A D0_A D1_A D2_A D3_A D4_A D5_A D6_A D7_A D8_A D9_A D10_A D11_A D12_A D13_A GND
Type 1 DO DO P P P P P P P P P P P P DI DI DI DO DO DO DO DO DO DO DO DO DO DO DO DO DO P
Description CCD Horizontal Clock 4 for Channel B CCD Reset Gate Clock for Channel B Digital Driver Ground for Channel B Digital Driver Supply for Channel B H1B to H4B Driver Ground for Channel B H1B to H4B Driver Supply for Channel B RG_B Driver Ground for Channel B RG_B Driver Supply for Channel B Analog Ground for Channel B Timing Core Analog Supply for Channel B Timing Core Analog Ground for Channel B Analog Ground for Channel B Digital Ground for Channel B Digital Supply for Channel B Vertical Sync Pulse for Channel B Horizontal Sync Pulse for Channel B Master Clock Input for Channel A Data Output Channel A Data Output Channel A Data Output Channel A Data Output Channel A Data Output Channel A Data Output Channel A Data Output Channel A Data Output Channel A Data Output Channel A Data Output Channel A Data Output Channel A Data Output Channel A Data Output Channel A Data Output Channel A Ground Connection
CLI_B D0_B D1_B D2_B D3_B D4_B D5_B D6_B D7_B D8_B D9_B D10_B D11_B D12_B D13_B
DI DO DO DO DO DO DO DO DO DO DO DO DO DO DO
Master Clock Input for Channel B Data Output Channel B Data Output Channel B Data Output Channel B Data Output Channel B Data Output Channel B Data Output Channel B Data Output Channel B Data Output Channel B Data Output Channel B Data Output Channel B Data Output Channel B Data Output Channel B Data Output Channel B Data Output Channel B
AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power.
Rev. A | Page 10 of 36
AD9942 TERMINOLOGY
Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes must be present over all operating conditions. Peak Nonlinearity Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9942 from a true straight line. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level 1 LSB and 0.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC's full-scale range. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC full scale/2n codes) where n is the bit resolution of the ADC. For the AD9942, 1 LSB is approximately 122.0 V. Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage. Matching Error The matching error refers to the Channel A to Channel B mismatch after post-ADC correction calibration has been applied to remove gain error between Channel A and Channel B. Crosstalk The crosstalk is measured while applying a full-scale step to one channel and measuring the interference on the opposite channel.
Interference (LSB) Crosstalk (dB) = 20 x log 16,384
Rev. A | Page 11 of 36
AD9942 EQUIVALENT INPUT/OUTPUT CIRCUITS
X = A, B.
AVDD
DVDD
R
330
05240-003
AVSS
AVSS
DVSS
Figure 3. CCDIN_X
Figure 6. Digital Inputs
HVDD OR RGVDD
DATA
AVDD
ENABLE DOUT
CLI
330
25k 1.4V +
05240-004
05240-006
AVSS
HVSS OR RGVSS
Figure 4. CLI_X
Figure 7. H1X to H4X and RG_X
DVSS
DRVDD
DATA
THREE-STATE
DOUT
DVSS
DRVSS
Figure 5. Data Outputs D0_X to D13_X
Rev. A | Page 12 of 36
05240-005
05240-007
AD9942 TYPICAL PERFORMANCE CHARACTERISTICS
1.0 1.015
CHANNEL A/CHANNEL B RATIO
-25C 1.010
+25C
0.5
LSB
0
1.005 +85C 1.000
05240-010
-0.5
05240-008
-1.0
0
4000
8000 12000 ADC OUTPUT CODE
16000
0.995
2000
4000
6000 8000 10000 12000 ADC OUTPUT CODE
14000
16000
Figure 8. DNL for Channel A and Channel B
Figure 10. Noncalibrated Channel A/Channel B Ratio
10
5
0
LSB
-5
-10
-15
05240-009
-20
2000
4000
6000 8000 10000 12000 DAC OUTPUT CODE
14000
16000
Figure 9. INL Performance for Channel A and Channel B
Rev. A | Page 13 of 36
AD9942 SYSTEM OVERVIEW
MAXIMUM FIELD DIMENSIONS
V DRIVER V1 > Vx, VSG1 > VSGx, SUBCK H1A TO H4A, RG_A H1B TO H4B, RG_B DOUT CCDIN_A CCD CCDIN_B
12-BIT HORIZONTAL = 4096 PIXELS MAX
AD9942
INTEGRATED HD_A, VD_A, AFE + TD HD_B, VD_B CLI_A, CLI_B SERIAL INTERFACE
05240-014
05240-015
DIGITAL IMAGE PROCESSING ASIC
12-BIT VERTICAL = 4096 LINES MAX
Figure 11. Typical Application
Figure 12. Vertical and Horizontal Counters
Figure 11 shows the typical system application diagram for the AD9942. The CCD output is processed by the AD9942 AFE circuitry, which consists of a CDS, a VGA, a CLPOB, and an ADC. The digitized pixel information is sent to the digital image processor chip, where all postprocessing and compression occurs. To operate the CCD, CCD timing parameters are programmed from the image processor to the AD9942 through the 6-wire serial interface. From the system master clock, CLI, which is provided by the image processor, the device generates the high speed CCD clocks and internal AFE clocks. All AD9942 clocks are synchronized with VD_X and HD_X. The CLPOB is programmed and generated internally.
The H drivers for H1A to H4A, H1B to H4B, RG_A, and RG_B are included in the AD9942, allowing these clocks to be directly connected to the CCD. An H driver voltage of 3 V is supported in the AD9942. Figure 12 shows the horizontal and vertical counter dimensions for the device. All internal horizontal clocking is programmed using these dimensions to specify line and pixel locations.
MAX VD LENGTH IS 4095 LINES VD_X
MAX HD LENGTH IS 4095 PIXELS
HD_X
Figure 13. Maximum VD_X/HD_X Dimensions
Rev. A | Page 14 of 36
05240-016
CLI_X
AD9942 SERIAL INTERFACE TIMING
All of the AD9942 internal registers are accessed through a 6-wire serial interface. Each register consists of an 8-bit address and a 24-bit data-word. Both the 8-bit address and the 24-bit data-word are written starting with the LSB. To write to each register, a 32-bit operation is required, as shown in Figure 14. Although many registers are less than 24 bits wide, all 24 bits must be written for each register. If the register is only 16 bits wide, then the upper 8 bits can be filled with 0s during the serial write operation. If fewer than 24 bits are written, the register is not updated with new data. Figure 15 shows a more efficient way to write to the registers by using the AD9942 address auto-increment capability. In this method, the lowest desired address is written first, followed by multiple 24-bit data-words. Each new 24-bit data-word is written automatically to the next highest register address. By eliminating the need to write each 8-bit address, faster register loading is achieved. The address auto-increment function can be used, starting with any register location, to write to as few as two registers or to as many as the entire register space.
8-BIT ADDRESS SDATA_X A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3
24-BIT DATA
... ...
D21
D22
D23
tDS
SCK_X 1 2 3 4 5 6
tDH
7 8 9 10 11 12 30 31 32
tLS
SL_X
tLH
... ...
SL UPDATED VD/HD UPDATED
VD_X
...
HD_X NOTES 1. X = A, B. 2. INDIVIDUAL SDATA_X BITS ARE LATCHED UPON SCK_X RISING EDGES. 3. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA. 4. IF THE REGISTER LENGTH IS <24 BITS, THEN DON'T CARE BITS MUST BE USEDTO COMPLETE THE 24-BIT DATA LENGTH. 5. NEW DATA IS UPDATED AT EITHER THE SL_X RISING EDGE OR AT THE HD_X FALLING EDGE AFTER THE NEXT VD_X FALLING EDGE. 6. VD_X/HD_X UPDATE POSITION CAN BE DELAYED TO ANY HD_X FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
Figure 14. Serial Write Operation
DATA FOR STARTING REGISTER ADDRESS SDATA_X A0 A1 A2 A3 A4 A5 A6 A7 D0 D1
DATA FOR NEXT REGISTER ADDRESS D23 D0 D1
... ... ...
D22
... ... ...
D22
D23
D0
D1
D2
SCK_X
1
2
3
4
5
6
7
8
9
10
31
32
33
34
55
56
57
58
59
SL_X
NOTES 1. X = A, B. 2. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY. 3. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS. 4. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN). 5. SL_X IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 6. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
05240-017
... ... ...
Figure 15. Continuous Serial Write Operation
Rev. A | Page 15 of 36
05240-018
AD9942
COMPLETE REGISTER LISTING
In Table 8 through Table 16, note the following:
* * *
All addresses and default values are expressed in hexadecimal format. All registers are VD_X/HD_X updated as shown in Figure 14, except for the registers indicated in Table 8, which are SL_X updated. Each channel is programmed independently using the 5-wire serial interface. Both channels can be programmed with the same register values by tying the SL_A and SL_B signals together and the SDATA_A and SDATA_B signals together.
Description AFE operation modes AFE control modes Software reset bit Reset bar signal for internal TG core Prevents update of registers VD/HD active edge Resets internal field pulse Retimes the HBLK to internal clock H1 polarity control RG signal control polarity Drive-strength control SHP/SHD sample control DOUT phase control
Table 8. Updated Registers upon Rising Edge of SL_X
Register OPRMODE CTLMODE SW_RESET TGCORE _RSTB PREVENTUPDATE VDHDEDGE FIELDVAL HBLKRETIME H1CONTROL RGCONTROL DRVCONTROL SAMPCONTROL DOUTPHASE
Table 9. CHN_A and CHN_B AFE Register Map
Address 00 01 02 03 04 05 Data Bit Content [11:0] [9:0] [7:0] [11:0] [17:0] [17:0] Default (Hex) 4 0 80 4 0 0 Name OPRMODE TESTMODE CLAMP LEVEL CTLMODE TESTMODE TESTMODE Description AFE operation modes (see Table 15). Internal test mode. Should always be set = 0. CLPOB level. AFE control modes (see Table 16). Test operation only. Set = 0. Test operation only. Set = 0.
Table 10. CHN_A and CHN_B Miscellaneous Register Map
Address 10 11 12 13 14 15 16 17 18 19 1A E8 Data Bit Content [0] [0] [0] [11:0] [0] [0] [1:0] [0] [1:0] [0] [0] [2:0] [11:3] Default (Hex) 0 0 0 0 0 0 0 0 0 0 0 0 Name SW_RST OUT_CONTROL TGCORE_RSTB UPDATE PREVENTUPDA TE VDHDEDGE FIELDVAL HBLKRETIME TEST MODE TEST MODE TEST MODE TEST MODE VGAGAIN Description Software reset.1 = reset all registers to default, then self-clear back to 0. Output control. 0 = make all dc outputs inactive. Timing core reset bar. 0 = reset TG core; 1 = resume operation. Serial update. Sets the line (HD) within the field to update serial data. Prevents the update of the VD-updated registers. 1 = prevent update. VD/HD active edge. 0 = falling edge triggered; 1 = rising edge triggered. Field value sync. 0 = next field 0; 1 = next field 1; 2/3 = next field 2. Retime HBLK to internal H1 clock. Preferred setting is 1. Setting to 1 adds one cycle delay to HBLK toggle positions. Internal test mode. Should always be set = 0. Internal test mode. Should always be set = 0. Internal test mode. Should always be set = 0. Internal test mode. Should always be set = 0. VGA gain control.
Rev. A | Page 16 of 36
AD9942
Table 11. CHN_A and CHN_B CLPOB Register Map
Address 20 21 22 23 24 25 26 27 28 Data Bit Content [3:0] [23:0] [23:0] [23:0] [23:0] [7:0] [11:0] [11:0] [11:0] Default (Hex) F FFFFFF FFFFFF FFFFFF FFFFFF 00 FFF FFF FFF Name CLPOBPOL CLPOBTOG_0 CLPOBTOG_1 CLPOBTOG_2 CLPOBTOG_3 CLPOBSPTR CLPOBSCP1 CLPOBSCP2 CLPOBSCP3 Description (the CLPOBSCP0 Always Starts at Line 0) Start polarities for CLPOB Sequences 0, 1, 2, and 3. Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. CLPOB sequence pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6]. CLPOB sequence--Change Position 1. CLPOB sequence--Change Position 2. CLPOB sequence--Change Position 3.
Table 12. PBLK Register Map
Address 30 31 32 33 34 35 36 37 38 Data Bit Content [3:0] [23:0] [23:0] [23:0] [23:0] [7:0] [11:0] [11:0] [11:0] Default (Hex) F FFFFFF FFFFFF FFFFFF FFFFFF 00 FFF FFF FFF Name PBLKPOL PBLKTOG_0 PBLKTOG_1 PBLKTOG_2 PBLKTOG_3 PBLKSPTR PBLKSCP1 PBLKSCP2 PBLKSCP3 Description (the PBLKSCP0 Always Starts at Line 0) Start polarities for PBLK Sequences 0, 1, 2, and 3. Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. PBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6]. PBLK sequence--Change Position 1. PBLK sequence--Change Position 2. PBLK sequence--Change Position 3.
Table 13. HBLK Register Map
Address 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 Data Bit Content [0] [0] [0] [3:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [7:0] [11:0] [11:0] [11:0] Default (Hex) 0 0 1 F FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF FFFFFF 00 FFF FFF FFF Name TESTMODE TESTMODE TESTMODE HBLKMASK HBLKTOG12_0 HBLKTOG34_0 HBLKTOG56_0 HBLKTOG12_1 HBLKTOG34_1 HBLKTOG56_1 HBLKTOG12_2 HBLKTOG34_2 HBLKTOG56_2 HBLKTOG12_3 HBLKTOG34_3 HBLKTOG56_3 HBLKSPTR HBLKSCP1 HBLKSCP2 HBLKSCP3 Description (the HBLKSCP0 Always Starts at Line 0) Test mode. Always set = 0 if accessed. Test mode. Always set = 0 if accessed. Test mode. Always set = 1 if accessed. HBLK internal masking polarity. 0 = mask H1 low; 1 = mask H1 high. Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 0. Toggle Position 3 [11:0] and Toggle Position 4 [23:12]. Sequence 0. Toggle Position 5 [11:0] and Toggle Position 6 [23:12]. Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 1. Toggle Position 3 [11:0] and Toggle Position 4 [23:12]. Sequence 1. Toggle Position 5 [11:0] and Toggle Position 6 [23:12]. Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 2. Toggle Position 3 [11:0] and Toggle Position 4 [23:12]. Sequence 2. Toggle Position 5 [11:0] and Toggle Position 6 [23:12]. Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. Sequence 3. Toggle Position 3 [11:0] and Toggle Position 4 [23:12]. Sequence 3. Toggle Position 5 [11:0] and Toggle Position 6 [23:12]. HBLK sequence pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6]. HBLK sequence--Change Position 1. HBLK sequence--Change Position 2. HBLK sequence--Change Position 3.
Rev. A | Page 17 of 36
AD9942
Table 14. CHN_A and CHN_B H1 to H4, RG, SHP, SHD Register Map
Address 60 Data Bit Content [12:0] Default (Hex) 01001 Name H1CONTROL Description H1 signal control. Polarity [0] (0 = inversion; 1 = no inversion). H1 positive edge location [6:1]. H1 negative edge location [12:7]. RG signal control. Polarity [0] (0 = inversion; 1 = no inversion). RG positive-edge location [6:1]. RG negative-edge location [12:7]. Drive-strength control for H1X [2:0], H2X [5:3], H3X [8:6], H4X [11:9], and RG_X [14:12]. Drive-current values: 0 = off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA. SHP/SHD sample control. SHP sampling location [5:0]. SHD sampling location [11:6]. DOUT phase control.
61
[12:0]
00801
RGCONTROL
62
[14:0]
0
DRVCONTROL
63 64
[11:0] [5:0]
00024 0
SAMPCONTROL DOUTPHASE
Table 15. CHN_A and CHN_B AFE Operation Register Detail
Address 00 Data Bit Content [1:0] [2] [3] [4] [5] [7:6] [8] [9] [11:10] Default (Hex) 0 1 0 0 0 0 0 0 0 Name PWRDOWN CLPENABLE CLPSPEED FASTUPDATE PBLK_LVL TEST MODE DCBYP TESTMODE TESTMODE Description 0 = normal operation; 1 = reference standby; 2/3 = total power-down. 0 = disable CLPOB; 1 = enable CLPOB. 0 = select normal CLPOB settling; 1 = select fast CLPOB settling. 0 = ignore VGA update; 1 = very fast clamping when VGA is updated. DOUT value during PBLK; 0 = blank to zero; 1 = blank to clamp level. Internal test mode. Should always be set = 3. 0 = enable dc restore circuit; 1 = bypass dc restore circuit during PBLK. Test operation only. Set = 0. Test operation only. Set = 0.
Table 16. CHN_A and CHN_B AFE Control Register Detail
Address 03 Data Bit Content [1:0] [2] [3] [4] [5] Default (Hex) 0 1 0 0 0 Name TESTMODE TESTMODE DOUTDISABLE DOUTLATCH GRAYENCODE Description Test operation only. Set = 0. Test operation only. Set = 0. 0 = data outputs are driven; 1 = data outputs are three-stated. 0 = latch data outputs with DOUT phase; 1 = output latch transparent. 0 = binary encode data outputs; 1 = gray encode data outputs.
Rev. A | Page 18 of 36
AD9942 CHANNEL A AND CHANNEL B PRECISION TIMING
HIGH SPEED TIMING GENERATION
The AD9942 generates flexible, high speed timing signals using the Precision Timing core for both channels. This core is the foundation for generating the timing used for both the CCD and the AFE, the reset gate RG_X, the horizontal drivers H1X to H4X, and the SHP/SHD sample clocks. A unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal CCD readout and the AFE correlated double sampling.
HIGH SPEED CLOCK PROGRAMMABILITY
Figure 17 shows how the high speed clocks, RG_X, H1X to H4X, SHP, and SHD, are generated. The RG_X pulse has programmable rising and falling edges and can be inverted using the polarity control. The horizontal clock, H1, has programmable rising and falling edges and polarity control. The H2 clock is always the inverse of the H1 clock. Table 17 summarizes the high speed timing registers and their parameters. Each edge location setting is six bits wide, but only 48 valid edge locations are available. Therefore, the register values are mapped into four quadrants, with each quadrant containing 12 edge locations. Table 18 shows the correct register values for the corresponding edge locations.
TIMING RESOLUTION
The Precision Timing core uses a 1x master clock input (CLI) as a reference. This clock should be the same as the CCD pixel clock frequency. Figure 16 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. Therefore, the edge resolution of the Precision Timing core is (tCLI/48). For more information on using the CLI input, see the Applications Information section.
POSITION CLI_X
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
tCLIDLY
1 PIXEL PERIOD
...
...
Figure 16. High Speed Clock Resolution from CLI
3 CCD SIGNAL 4
1 RG_X 5 H1X/H3X
2
6
H2X/H4X PROGRAMMABLE CLOCK POSITIONS:
1 RG_X RISING EDGE. 2 RG_X FALLING EDGE. 3 SHP SAMPLE LOCATION. 4 SHD SAMPLE LOCATION. 5 H1X/H3X RISING EDGE POSITION. 6 H1X/H3X FALLING EDGE POSITION
(H2X/H4X ARE INVERSE OF H1X/H3X).
Figure 17. High Speed Clock Programmable Locations
Rev. A | Page 19 of 36
05240-020
05240-019
NOTES 1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. 2. THERE IS A FIXED DELAY FROM THE CLI_X INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6ns TYP).
AD9942
Table 17. Channel A and Channel B H1X to H4X CONTROL, RG_X CONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters
Parameter Polarity Positive Edge Negative Edge Sample Location Drive Control DOUT Phase Length (Bit) 1 6 6 6 3 6 Range High/low 0 to 47 edge locations 0 to 47 edge locations 0 to 47 sample locations 0 to7 current steps 0 to 47 edge locations Description Polarity control for H1X and RG_X (0 = no inversion; 1 = inversion). Positive-edge location for H1X, H3X, and RG_X. Negative-edge location for H1X and RG_X. Sampling location for SHP and SHD. Drive current for H1X to H4X and RG_X outputs, 0 to 7 steps of 4.1 mA each. Phase location of data outputs with respect to pixel period.
Table 18. Channel A and Channel B Precision Timing Edge Locations
Quadrant I II III IV Edge Location (Decimal) 0 to 11 12 to 23 24 to 35 36 to 47 Register Value (Decimal) 0 to 11 16 to 27 32 to 43 48 to 59 Register Value (Binary) 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011
Rev. A | Page 20 of 36
AD9942
H DRIVER AND RG OUTPUTS
In addition to the programmable timing positions, the AD9942 features on-chip output drivers for the RG_X and H1X to H4X outputs. These drivers are powerful enough to drive the CCD inputs directly. The H-driver and RG-driver currents can be adjusted for optimum rise and fall time into a particular load by using the DRVCONTROL register (Address 0x62). The DRVCONTROL register is divided into five 3-bit values, each adjustable in 4.1 mA increments. The minimum setting of 0 is equal to off, or three-state, and the maximum setting of 7 is equal to 30.1 mA. As shown in Figure 18, the H2X/H4X outputs are inverses of H1X. The internal propagation delay resulting from the signal inversion is less than l ns, which is significantly less than the typical rise time driving the CCD load. This results in a H1X/H2X crossover voltage at approximately 50% of the output swing. The crossover voltage is not programmable.
DIGITAL DATA OUTPUTS
The AD9942 data output phase is programmable using the DOUTPHASE register (Address 0x64). Any edge from 0 to 47 can be programmed, as shown in Figure 19. The pipeline delay for the digital data output is shown in Figure 20.
H1X/H3X
tRISE
H2X/H4X
tPD << tRISE
H1X/H3X FIXED CROSSOVER VOLTAGE
tPD
H2X/H4X
05240-021
Figure 18. H-Clock Inverse Phase Relationship
P[0] CLI_X 1 PIXEL PERIOD
P[12]
P[24]
P[36]
P[48] = P[0]
tOD
DOUT
Figure 19. Digital Output Phase Adjustment
VD_X
HD_X
H-COUNTER RESET
CLI_X
H COUNTER X (PIXEL COUNTER)
X
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
0
05240-022
NOTES 1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. 2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
1
2
3
05240-023
NOTES 1. INTERNAL H COUNTER IS RESET SEVEN CLI_X CYCLES AFTER THE HD_X FALLING EDGE (WHEN USING VDHDEDGE = 0). 2. TYPICAL TIMING RELATIONSHIP: CLI_X RISING EDGE IS COINCIDENT WITH HD_X FALLING EDGE.
Figure 20. Pipeline Delay for Channel A and Channel B Digital Data Output
Rev. A | Page 21 of 36
AD9942 CHANNEL A AND CHANNEL B HORIZONTAL CLAMPING AND BLANKING
The AD9942 horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Individual sequences are defined for each signal, which are then organized into multiple regions during image readout. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate different image transfer timing and high speed line shifts.
INDIVIDUAL HBLK SEQUENCES
The HBLK programmable timing, shown in Figure 22, is similar to CLPOB and PBLK. However, there is no start polarity control. Only the toggle positions are used to designate the start and stop positions of the blanking period. Additionally, there is a polarity control, HBLKMASK, which designates the polarity of the horizontal clock signal H1 during the blanking period. Setting HBLKMASK high sets H1 low and H2 high during the blanking, as shown in Figure 23. Up to four individual sequences are available for HBLK.
INDIVIDUAL CLPOB AND PBLK SEQUENCES
The AFE horizontal timing consists of CLPOB and PBLK, as shown in Figure 21. These two signals are independently programmed using the parameters shown in Table 19. The start polarity, first toggle position, and second toggle position are fully programmable for each signal. The CLPOB and PBLK signals are active low and should be programmed accordingly. Up to four individual sequences can be created for each signal.
Table 19. Channel A and Channel B CLPOB and PBLK Individual Sequence Parameters
Parameter Polarity Toggle Position 1 Toggle Position 2 Length (Bit) 1 12 12 Range High/low 0 to 4095 pixel locations 0 to 4095 pixel locations Description Starting polarity of CLPOB and PBLK pulses for Sequences 0 to 3. First toggle position within the line for Sequences 0 to 3. Second toggle position within the line for Sequences 0 to 3.
Rev. A | Page 22 of 36
AD9942
...
HD 2 CLPOB PBLK 1 ACTIVE 3 ACTIVE
...
Figure 21. CLPOB and PBLK Pulse Placement
...
HD_X 1 HBLK BLANK 2 BLANK
...
05240-025
1 FIRST TOGGLE POSITION = START OF BLANKING. 2 SECOND TOGGLE POSITION = END OF BLANKING.
PROGRAMMABLE SETTINGS:
Figure 22. HBLK Pulse Placement
...
HD_X
...
HBLK
H1X/H3X
THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1).
...
H1X/H3X H2X/H3X
05240-024
PROGRAMMABLE SETTINGS: 1 START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW). 2 FIRST TOGGLE POSITION. 3 SECOND TOGGLE POSITION.
...
Figure 23. HBLK Masking Control
Rev. A | Page 23 of 36
05240-026
AD9942 CHANNEL A AND CHANNEL B SPECIAL HBLK PATTERNS
Six toggle positions are available for HBLK. Typically, only two of the toggle positions are used to generate the standard HBLK interval. However, the additional toggle positions can be used to generate special HBLK patterns, as shown in Figure 24. The pattern in this example uses all six toggle positions to generate two extra groups of pulses during the HBLK interval. By changing the toggle positions, different patterns can be created. into four separate regions, as shown in Figure 25. The SCP0 is always hard-coded to Line 0, and SCP1 to SCP3 are register programmable. During each region bounded by the SCP, the SPTR registers designate which sequence is used by each signal. CLPOB, PBLK, and HBLK each have a separate set of SCPs. For example, CLPOBSCP1 defines Region 0 for CLPOB, and in that region any of the four CLPOB sequences can be selected with the CLPOBSPTR register. The next SCP defines a new region, in which each signal can be assigned to a different individual sequence. The sequence control registers are detailed in Table 21.
HORIZONTAL SEQUENCE CONTROL
The AD9942 uses sequence change positions (SCPs) and sequence pointers (SPTRs) to organize the individual horizontal sequences. Up to four SCPs are available to divide the readout
TOG1
TOG2
TOG3
TOG4
TOG5
TOG6
HBLK
H1X/H3X
H2X/H4X
05240-027
05240-028
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS.
Figure 24. Generating Special HBLK Patterns
SEQUENCE CHANGE OF POSITION 0 (V COUNTER = 0)
SINGLE FIELD (1 VD INTERVAL) CLAMP AND PBLK SEQUENCE REGION 0
SEQUENCE CHANGE OF POSITION 1 CLAMP AND PBLK SEQUENCE REGION 1 SEQUENCE CHANGE OF POSITION 2
CLAMP AND PBLK SEQUENCE REGION 2
SEQUENCE CHANGE OF POSITION 3
CLAMP AND PBLK SEQUENCE REGION 3
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
Figure 25. CLPOB and PBLK Sequence Flexibility
Rev. A | Page 24 of 36
AD9942
Table 20. Channel A and Channel B HBLK Individual Sequence Parameters
Parameter HBLKMASK Toggle Position 1 Toggle Position 2 Toggle Position 3 Toggle Position 4 Toggle Position 5 Toggle Position 6 Length (Bit) 1 12 12 12 12 12 12 Range High/low 0 to 4095 pixel locations 0 to 4095 pixel locations 0 to 4095 pixel locations 0 to 4095 pixel locations 0 to 4095 pixel locations 0 to 4095 pixel locations Description Masking polarity for H1 for Sequences 0 to 3 (0 = low; 1 = high). First toggle position within the line for Sequences 0 to 3. Second toggle position within the line for Sequences 0 to 3. Third toggle position within the line for Sequences 0 to 3. Fourth toggle position within the line for Sequences 0 to 3. Fifth toggle position within the line for Sequences 0 to 3. Sixth toggle position within the line for Sequences 0 to 3.
Table 21. Channel A and Channel B Horizontal Sequence Control Registers for CLPOB, PBLK, and HBLK
Register SCP SPTR Length (Bit) 12 2 Range 0 to 4095 line numbers 0 to 3 sequence numbers Description CLPOB/PBLK/HBLK SCP to define Horizontal Regions 0 to 3. Sequence pointer for Horizontal Regions 0 to 3.
Table 22. Channel A and Channel B External HBLK Register Parameters
Register HBLKDIR HBLKPOL HBLKEXTMASK Length (Bit) 1 1 1 Range High/low High/low High/low Description Specifies HBLK internally generated or externally supplied. 0 = internal; 1 = external. External HBLK active polarity. 0 = active low; 1 = active high. External HBLK masking polarity. 0 = mask H1 low; 1 = mask H1 high.
H-COUNTER SYNCHRONIZATION
The H-counter reset occurs seven CLI cycles after the HD falling edge.
VD_X
HD_X
H-COUNTER RESET
CLI_X
H COUNTER X (PIXEL COUNTER)
X
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
0
1
2
3
05240-029
NOTES 1. INTERNAL H COUNTER IS RESET SEVEN CLI_X CYCLES AFTER THE HD_X FALLING EDGE (WHEN USING VDHDEDGE = 0). 2. TYPICAL TIMING RELATIONSHIP: CLI_X RISING EDGE IS COINCIDENT WITH HD_X FALLING EDGE.
Figure 26. H-Counter Synchronization
Rev. A | Page 25 of 36
AD9942 CHANNEL A AND CHANNEL B POWER-UP PROCEDURE
When the AD9942 is powered up, the following sequence is recommended for Channel A and Channel B (see Figure 27 for each step). 1. 2. 3. Turn on the power supplies for the AD9942. Apply the master clock input, CLI_X, VD_X, and HD_X. Although the AD9942 contains an on-chip power-on reset, a software reset of the internal registers is recommended. Write a 1 to the SW_RST register (Address 0x10), which resets all the internal registers to their default values. This bit is self-clearing and is automatically reset to 0. Reset the Precision Timing core by writing a 0 to the TGCORE_RSTB register (Address 0x12), then write a l to the TGCORE_RSTB register. This starts the internal timing core operation. 7. 8. 5. 6. Write a 1 to the PREVENTUPDATE register (Address 0x14). This prevents an update of the serial register data. Write to the desired registers to configure high speed timing and horizontal timing. Write a 3 to the [7:6] TESTMODE register (Address 0x00). See Table 15. Write a 1 to the OUT_CONTROL register (Address 0x11). This allows the outputs to become active after the next VD_X/HD_X rising edge. Write a 0 to the PREVENTUPDATE register (Address 0x14). This allows the serial information to be updated at the next VD_X/HD_X falling edge. The next VD_X/HD_X falling edge allows register updates, including updates of OUT_CONTROL, to occur which enables all clock outputs.
9.
4.
VDD (INPUT)
1
CLI_X (INPUT)
2
tPWR
SERIAL WRITES
3
4
5
6
7
8
VD_X (OUTPUT) 2 HD_X (OUTPUT) H2X/H4X DIGITAL OUTPUTS H1X/H3X, RG_X
... ...
9 ODD FIELD 1H
1V
... ...
EVEN FIELD
CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS UPDATED AT VD/HD EDGE
Figure 27. Recommended Power-Up Sequence
Rev. A | Page 26 of 36
05240-030
AD9942 CHANNEL A AND CHANNEL B ANALOG FRONT END OPERATION
The AD9942 signal processing chain is shown in Figure 28. Each processing step is essential for achieving a high quality image from the raw CCD pixel data.
CORRELATED DOUBLE SAMPLER
The CDS circuit samples each CCD pixel twice to extract the video information and reject low frequency noise. The timing shown in Figure 17 illustrates how the two internally generated CDS clocks, SHP and SHD, are used to sample the reference level and the CCD signal level, respectively. The placement of the SHP and SHD sampling edges is determined by the setting of the SAMPCONTROL register located at Address 0x63. Placement of these two clock signals is critical for achieving the best performance from the CCD.
DC RESTORE
To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 F series coupling capacitor. This restores the dc level of the CCDIN_X signal to approximately 1.5 V to be compatible with the 3 V supply voltage of the AD9942.
1.0F 1.0F REFB_X DC RESTORE 1.5V SHP SHD CCDIN_X 1.0F OPTICAL BLACK CLAMP CLPOB PBLK DIGITAL FILTER SHP DOUT SHD PHASE CLPOB PBLK 8 CLAMP LEVEL REGISTER PRECISION TIMING GENERATION V-H TIMING GENERATION 0dB ~ 18dB VGA1 1.0V REFT_X 2.0V
AD9942
INTERNAL VREF 2V FULL SCALE OUTPUT DATA LATCH 14 DOUT PHASE
CDS
ADC
DOUT
VGA GAIN REGISTERS
DAC
Figure 28. Channel A and Channel B Analog Front End Functional Block Diagram
Rev. A | Page 27 of 36
05240-031
AD9942
CHANNEL A AND CHANNEL B VARIABLE GAIN AMPLIFIER
The VGA stage provides a gain range of 0 dB to 18 dB, programmable with 9-bit resolution through the serial digital interface. A minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. The VGA gain curve follows a linear-in-dB characteristic. The exact VGA gain can be calculated for any gain register value by using the equation Gain (dB) = (0.035 x VGAGAIN Code) where the code range is 0 to 511.
20 18 16 14
GAIN (dB)
CHANNEL A AND CHANNEL B CLPOB
The CLPOB loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD black level. During the optical black (OB), or shielded, pixel interval on each line, the ADC output is compared with a fixed black level reference, selected by the user in the CLAMP LEVEL register. The value can be programmed between 0 LSB and 255 LSB in 256 steps. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a digital-to-analog converter. Typically, the CLPOB loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during postprocessing, the AD9942 CLPOB can be disabled using Bit D2 in the OPRMODE register. The CLAMP LEVEL register can be used to provide programmable offset adjustment even when the loop is disabled. The CLPOB pulse should be placed during the CCD's OB pixel region. It is recommended that the CLPOB pulse duration be at least 20 pixels wide to minimize clamp noise. Shorter pulse widths can be used, but clamp noise might increase and the ability to track low frequency variations in the black level is reduced. See the Channel A and Channel B Horizontal Clamping and Blanking section and the Applications Information section for timing examples.
12 10 8 6 4 2 0 0 50 100 150 200 250 300 350 GAIN CODE (Decimal) 400 450 500
05240-032
CHANNEL A AND CHANNEL B DIGITAL DATA OUTPUTS
The AD9942 digital output data is latched using the DOUTPHASE register value, as shown in Figure 28. (Output data timing is shown in Figure 19 and Figure 20.) It is also possible to leave the output latches transparent, so that the data outputs are valid immediately from the ADC. Programming the AFE Control Register Bit D4 to 1 sets the output latches transparent. The data outputs can also be disabled (three-stated) by setting the AFE Control Register Bit D3 to 1. The data output coding is typically straight binary, but the coding can be changed to gray coding by setting the AFE Control Register Bit D5 to 1.
Figure 29. VGA Gain Curve
CHANNEL A AND CHANNEL B ADC
The AD9942 uses a high performance ADC architecture, optimized for high speed and low power. Differential nonlinearity (DNL) performance is typically better than 0.5 LSB. The ADC uses a 2 V input range. See Figure 8 and Figure 9 for typical linearity and noise performance plots for the AD9942.
Rev. A | Page 28 of 36
AD9942 APPLICATIONS INFORMATION
CIRCUIT CONFIGURATION
The AD9942 recommended circuit configuration is shown in Figure 30. Achieving good image quality from the AD9942 requires careful attention to the printed circuit board (PCB) layout. All signals should be routed to maintain low noise performance. The CCD_A and CCD_B output signals should be directly routed to Pins A1 and A7, respectively, through a 0.1 F capacitor. The master clock, CLI_X, should be carefully routed to Pins A3 and A9 to minimize interference with the CCDIN_X, REFT_X, and REFB_X signals. The digital outputs and clock inputs should be connected to the digital ASIC away from the analog and CCD clock signals. Placing series resistors close to the digital output pins may help to reduce digital code transition noise. If the digital outputs must drive a load larger than 20 pF, buffering is recommended to minimize additional noise. If the digital ASIC can accept gray code, the AD9942 outputs can be selected to output data in gray code format using the Control Register Bit D5. Gray coding helps reduce potential digital transition noise compared with binary coding. The H1X to H4X and RG_X traces should have low inductance to avoid excessive distortion of the signals. Heavier traces are recommended because of the large transient current demand on H1X to H4X from the capacitive load of the CCD. If possible, physically locate the AD9942 closer to the CCD to reduce the inductance on these lines. As always, the routing path should be as direct as possible from the AD9942 to the CCD. The CLI_X and CCDIN_X PCB traces should be carefully matched in length and impedance to achieve optimal channelto-channel matching performance.
GROUNDING/DECOUPLING RECOMMENDATIONS
As Figure 30 shows, a single ground plane is recommended for the AD9942. This ground plane should be as continuous as possible, particularly around the P-, AI-, and A-type pins, to ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. All high frequency decoupling capacitors should be located as close as possible to the package pins. All the supply pins must be decoupled to ground with good quality, high frequency chip capacitors. There should also be a 4.7 F or larger bypass capacitor for each main supply--that is, the AVDD_X, RGVDD_X, HVDD_X, and DRVDD_X-- although this is not necessary for each individual pin. In most applications, it is easier to share the supply for RGVDD_X and HVDD_X, which can be done as long as the individual supply pins are separately bypassed. A separate 3 V supply can be used for DRVDD_X, but this supply pin should still be decoupled to the same ground plane as the rest of the chip. A separate ground for DRVSS_X is not recommended. The reference bypass pins (REFT_X, REFB_X) should be decoupled to ground as close as possible to their respective pins. The analog input capacitor (CCDIN_X) should also be located close to the pin. The GND connections should be tied to the lowest impedance ground plane on the PCB. Performance does not degrade if several of these GND connections are left unconnected for routing purposes.
Rev. A | Page 29 of 36
AD9942
3V ANALOG SUPPLY RG_A OUTPUT RG_A DRIVER SUPPLY 4.7F + + 3V ANALOG SUPPLY RG_B OUTPUT RG_B DRIVER SUPPLY
COMMON MASTER CLOCK INPUT
0.1F 0.1F 0.1F 0.1F
4.7F 4.7F
0.1F
3V ANALOG SUPPLY
+
COMMON MASTER CLOCK INPUT
RGVDD_A RGVDD_B RGVSS_A TCVDD_B RGVSS_B TCVDD_A TCVSS_A TCVSS_B AVDD_B
AVDD_A
AVSS_A
CLI_A
RG_B
CLI_B
RG_A
GND
GND
GND
GND
GND
GND
GND
GND
E5
B1
A2
A3
C3
C4
B4
A4
B3
A5
B5
C5
D5
E6
GND
D6
C6
B6
A6
GND
0.1F
4.7F
+
3V ANALOG SUPPLY
B9
A9
A10
B10
CHN_A CCD SIGNAL
CCDIN_A 0.1F 1.0F 1.0F REFB_A REFT_A SL_A SDATA_A SCK_A HD_A VD_A HVDD_A
C10
A8
C9
A1 D1 C1 B2 C2 D2 E1 E2 E4 E3 F4 F3 D4 D3 F1 F2 G1 H1 J1 K1 G2 H2 K2 G3 H3
G10 H10 K10 J10 G4 G5 G6 K4 H4 K3 H5 K5 K6 H6 K9 H9 F5 F6 J3 J4 J2 J5 J6 J8 J9
B7 A7 D7 C7 B8 C8 D8 E7 E8 E10 E9 F10
AVSS_B CCDIN_B REFB_B REFT_B SL_B SDATA_B SCK_B HD_B VD_B HVDD_B HVSS_B H1B H2B H3B H4B DVDD_B DVSS_B D0_B (LSB) D1_B D2_B D3_B D4_B D5_B D6_B D7_B 0.1F 3V ANALOG SUPPLY 3 HD COMMON INPUT VD COMMON INPUT 0.1F 4 4.7F SERIAL INTERFACE FOR CHN_B H1B TO H4B DRIVER SUPPLY 0.1F 1.0F 1.0F CHN_B CCD SIGNAL
SERIAL INTERFACE FOR CHN_A
HD COMMON INPUT H1A TO H4A DRIVER SUPPLY VD COMMON INPUT 4.7F
0.1F HVSS_A H1A TO H4A 4 H1A OUTPUTS H2A H3A H4A
AD9942
F9 D10 D9 F7 F8 G7 H7 J7 K7 G8 H8 K8 G9
H1B TO H4B OUTPUTS
3V ANALOG SUPPLY
DVDD_A 0.1F DVSS_A D0_A (LSB) D1_A D2_A D3_A D4_A D5_A D6_A D7_A D8_A
D13_B (MSB)
GND
GND
GND
GND
GND
GND
GND
GND
GND
D11_A
GND
DRVSS_A
D13_A (MSB)
DRVSS_B
D11_B
D9_A
D9_B
DRVDD_A
DRVDD_B
D10_A
D12_A
D12_B
0.1F
CHN_A DATA OUTPUTS
14
0.1F
D10_B
D8_B
14
CHN_B DATA OUTPUTS
4.7F +
4.7F +
3V DRIVER
3V DRIVER
Figure 30. Recommended Circuit Configuration
Rev. A | Page 30 of 36
05240-033
AD9942
DRIVING THE CLI INPUT
The AD9942 CLI can be used in two configurations, depending on the application. Figure 31 shows a typical dc-coupled input from the master clock source. When the dc-coupled technique is used, the master clock signal should be at standard 3 V CMOS logic levels. As shown in Figure 32, a 1000 pF ac coupling capacitor can be used between the clock source and the CLI input. In this configuration, the CLI input performs a self-bias to the proper dc voltage level of approximately 1.4 V. When the accoupled technique is used, the master clock signal can be as low as 500 mV in amplitude. 10 OB lines at the front of the readout and 2 at the back of the readout. The horizontal direction has 4 OB pixels in the front and 48 in the back. To configure the AD9942 horizontal signals for this CCD, three sequences can be used. Figure 34 shows the first sequence to be used during vertical blanking. During this time, there are no valid OB pixels from the sensor, so the CLPOB signal is not used. PBLK can be enabled during this time because no valid data is available. Figure 35 shows the recommended sequence for the vertical OB interval. The clamp signals are used across the whole lines to stabilize the clamp loop of the AD9942. Figure 36 shows the recommended sequence for the effective pixel readout. The 48 OB pixels at the end of each line are used for the CLPOB signal.
AD9942
CLI_X LPF 1nF
05240-034
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 33 shows an example CCD configuration. The horizontal register contains 28 dummy pixels, which occur on each line clocked from the CCD. In the vertical direction, there are
AD9942
CLI_X ASIC
ASIC
MASTER CLOCK
Figure 31. CLI Connection, DC-Coupled
Figure 32. CLI Connection, AC-Coupled
SEQUENCE 2 (OPTIONAL)
2 VERTICAL OB LINES
V
EFFECTIVE IMAGE AREA
USE SEQUENCE 3
10 VERTICAL OB LINES
USE SEQUENCE 2 H 4 OB PIXELS HORIZONTAL CCD REGISTER
05240-036
48 OB PIXELS
28 DUMMY PIXELS
Figure 33. Example CCD Configuration
Rev. A | Page 31 of 36
05240-035
MASTER CLOCK
AD9942
SEQUENCE 1: VERTICAL BLANKING LINES CCDIN SHP SHD H1X/H3X H2X/H4X HBLK CLPOB
05240-037
INVALID PIX
VERTICAL SHIFT
DUMMY
INVALID PIXELS
VERT SHIFT
Figure 34. Horizontal Sequence During Vertical Blanking
SEQUENCE 2: VERTICAL OPTICAL BLACK LINES OPTICAL BLACK CCDIN SHP SHD H1X/H3X H2X/H4X HBLK CLPOB VERTICAL SHIFT DUMMY OPTICAL BLACK VERT SHIFT
Figure 35. Horizontal Sequences During Vertical OB Pixels
SEQUENCE 3: EFFECTIVE PIXEL LINES OPTICAL BLACK CCDIN SHP SHD H1X/H3X H2X/H4X HBLK CLPOB VERTICAL SHIFT OPTICAL BLACK DUMMY EFFECTIVE PIXELS OPTICAL BLACK VERT SHIFT
Figure 36. Horizontal Sequences During Effective Pixels
Rev. A | Page 32 of 36
05240-039
05240-038
AD9942 OUTLINE DIMENSIONS
9.10 9.00 SQ 8.90 A1 CORNER INDEX AREA
10 9 87 65 43 21 A B
BALL A1 PAD CORNER TOP VIEW
C
7.20 BSC SQ
D E F G H J K
0.80 BSC DETAIL A 1.40 MAX
DETAIL A
0.65 MIN
0.25 MIN 0.55 0.50 0.45 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-205-AB. COPLANARITY 0.12
SEATING PLANE
Figure 37. 100-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-100-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9942BBCZ 1 AD9942BBCZRL1
1
Temperature Range -25C to +85C -25C to +85C
Package Description 100-Lead Chip Scale Package Ball Grid Array [CSP_BGA] 100-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
Package Option BC-100-1 BC-100-1
Z = Pb-free part.
Rev. A | Page 33 of 36
AD9942 NOTES
Rev. A | Page 34 of 36
AD9942 NOTES
Rev. A | Page 35 of 36
AD9942 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05240-0-8/06(A)
Rev. A | Page 36 of 36

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